• 本当は、田舎に庵を建てて隠遁生活したいけど、先立つものも無いので自宅で..。

FPGAで遊ぶ 7セグ点灯

Basys3搭載されている7セグメントディスプレイを点灯させるプログラムを作成しました。

4個の7セグはアノードが共通になっているので、ダイナミック点灯させる必要があります。 ダイナミック点灯のリフレッシュレートは、1ms~16msが適当とマニュアルにあるので、20bitのカウンターで10.5msのクロックを作成しました。 

点灯させるための信号は、アノード、セグメントともアクティブローになっています。 

16個のスイッチの状態を読み込んで、4桁の16進数を7セグに表示する機能をプログラムしました。

ソースです。


module Decoder(
input CLK,
input RST,
input [15:0] SWITCH,
output reg[6:0] SEG,
output reg DP,
output reg [3:0] AN
);

function [6:0] segdec;
input [3:0] sldsw;
begin
case(sldsw) //low active
4’h0: segdec = 7’b1000000;
4’h1: segdec = 7’b1111001;
4’h2: segdec = 7’b0100100;
4’h3: segdec = 7’b0110000;
4’h4: segdec = 7’b0011001;
4’h5: segdec = 7’b0010010;
4’h6: segdec = 7’b0000010;
4’h7: segdec = 7’b1111000;
4’h8: segdec = 7’b0000000;
4’h9: segdec = 7’b0010000;
4’ha: segdec = 7’b0001000;
4’hb: segdec = 7’b0000011;
4’hc: segdec = 7’b1000110;
4’hd: segdec = 7’b0100001;
4’he: segdec = 7’b0000110;
4’hf: segdec = 7’b0001110;
default: segdec = 7’b11111111;
endcase
end
endfunction

wire one_ms;

//1.3ms clk refresh rate 1-16ms
reg[19:0] cnt1m;

always @(posedge CLK) begin
if(RST) cnt1m <= 1’h0;
else cnt1m <= cnt1m + 1’h1;
end

assign one_ms = (cnt1m == 20’hfffff);

//AN Counter
reg[1:0] an_cnt;

always @(posedge one_ms or posedge RST) begin
if(RST) an_cnt <= 1’h0;
else an_cnt <= an_cnt + 1’h1;
end

always @(posedge one_ms) begin
case(an_cnt)
4’h0: begin
SEG <= segdec(SWITCH[3:0]);
AN <= 4’he;
end
4’h1: begin
SEG <= segdec(SWITCH[7:4]);
AN <= 4’hd;
end
4’h2: begin
SEG <= segdec(SWITCH[11:8]);
AN <= 4’hb;
end
4’h3: begin
SEG <= segdec(SWITCH[15:12]);
AN <= 4’h7;
end
default begin
SEG = 6’h0;
AN <= 4’hf;
end
endcase
end
endmodule


制約ファイルです。


##Clock signal
set_property PACKAGE_PIN W5 [get_ports {CLK}]
set_property IOSTANDARD LVCMOS33 [get_ports {CLK}]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK}]

##Switches
set_property PACKAGE_PIN V17 [get_ports {SWITCH[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SWITCH[0]}]
set_property PACKAGE_PIN V16 [get_ports {SWITCH[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SWITCH[1]}]
set_property PACKAGE_PIN W16 [get_ports {SWITCH[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SWITCH[2]}]
set_property PACKAGE_PIN W17 [get_ports {SWITCH[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SWITCH[3]}]
set_property PACKAGE_PIN W15 [get_ports {SWITCH[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SWITCH[4]}]
set_property PACKAGE_PIN V15 [get_ports {SWITCH[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SWITCH[5]}]
set_property PACKAGE_PIN W14 [get_ports {SWITCH[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SWITCH[6]}]
set_property PACKAGE_PIN W13 [get_ports {SWITCH[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SWITCH[7]}]
set_property PACKAGE_PIN V2 [get_ports {SWITCH[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SWITCH[8]}]
set_property PACKAGE_PIN T3 [get_ports {SWITCH[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SWITCH[9]}]
set_property PACKAGE_PIN T2 [get_ports {SWITCH[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SWITCH[10]}]
set_property PACKAGE_PIN R3 [get_ports {SWITCH[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SWITCH[11]}]
set_property PACKAGE_PIN W2 [get_ports {SWITCH[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SWITCH[12]}]
set_property PACKAGE_PIN U1 [get_ports {SWITCH[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SWITCH[13]}]
set_property PACKAGE_PIN T1 [get_ports {SWITCH[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SWITCH[14]}]
set_property PACKAGE_PIN R2 [get_ports {SWITCH[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SWITCH[15]}]

##7 segment display
set_property PACKAGE_PIN W7 [get_ports {SEG[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SEG[0]}]
set_property PACKAGE_PIN W6 [get_ports {SEG[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SEG[1]}]
set_property PACKAGE_PIN U8 [get_ports {SEG[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SEG[2]}]
set_property PACKAGE_PIN V8 [get_ports {SEG[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SEG[3]}]
set_property PACKAGE_PIN U5 [get_ports {SEG[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SEG[4]}]
set_property PACKAGE_PIN V5 [get_ports {SEG[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SEG[5]}]
set_property PACKAGE_PIN U7 [get_ports {SEG[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SEG[6]}]

set_property PACKAGE_PIN V7 [get_ports {DP}]
set_property IOSTANDARD LVCMOS33 [get_ports {DP}]

set_property PACKAGE_PIN U2 [get_ports {AN[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {AN[0]}]
set_property PACKAGE_PIN U4 [get_ports {AN[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {AN[1]}]
set_property PACKAGE_PIN V4 [get_ports {AN[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {AN[2]}]
set_property PACKAGE_PIN W4 [get_ports {AN[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {AN[3]}]

##Buttons
set_property PACKAGE_PIN U18 [get_ports {RST}]
set_property IOSTANDARD LVCMOS33 [get_ports {RST}]


テストベンチです。


module sim_Decoder;

localparam STEP = 8;

reg clk;
reg rst;
reg [15:0] switch;
wire [6:0] seg;
wire [3:0] an;

Decoder Decoder(
.CLK (clk),
.RST (rst),
.SWITCH (switch),
.SEG (seg),
.DP (),
.AN (an)
);

always begin
clk = 1’h0;
#(STEP/2);
clk = 1’h1;
#(STEP/2);
end

initial begin
rst = 1’h0;
#(STEP*10);
rst = 1’h1;
#(STEP*100);
rst = 1’h0;
switch = 16’h1234;
#(STEP*20000);
$stop;
end

endmodule


結構、チカチカしますが機能的には正常に動作しました。

コメントを残す

メールアドレスが公開されることはありません。 が付いている欄は必須項目です

CAPTCHA